Interface circuit and signal clamping circuit using level-down shifter

ABSTRACT

Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application Nos.2003-50268, filed on Jul. 22, 2003, and 2003-84196, filed on 25 Nov.2003 in the Korean Intellectual Property Office, the disclosure of bothapplications are hereby incorporated by reference in their entirety.Additionally, this application is a divisional of U.S. application Ser.No. 10/890,493 filed on Jul. 13, 2004, which is fully incorporatedherein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit, andmore particularly, to an interface circuit including a level-downshifter.

2. Discussion of the Related Art

For semiconductor devices used in mobile products, low power consumptionis an important characteristic. In general, semiconductor integratedcircuits (ICs) require an external power source to provide power tooperate. Typically, the external power source is pulled down to aninternal power and the internal power is used to operate the IC or chip.For example, semiconductor ICs receive an external power of about 3.3Vand generate an internal power of about 1.8V to about 2.2V. An interfacecircuit is needed to handle a voltage difference between a circuitoperating at 3.3V and a circuit operating at 1.8V. The interface circuitis generally used in an input buffer circuit or an output buffer circuitthat is interfaced with the outside.

FIG. 1 shows signal transmission between a first circuit 110 operatingat an external power of about 3.3V and second circuit 120 operating atan internal power of about 1.8V. An input signal IN that undergoes fullswing from 0V to 3.3V is input to the first circuit 110. For convenienceof explanation, it is understood that the first circuit 110 and thesecond circuit 120 perform simple inverting operation. The first circuit110 inverts the input signal IN and outputs the inverted IN signal to afirst node NA and the second circuit 120 in turn inverts the invertingsignal at NA and outputs the resulting signal to a second node NB.

Here, referring to a signal waveform of the first node NA and a signalwaveform of the second node NB, the first node NA transits from a logichigh level to a logic low level by swinging from about 3.3V to 0V andtransits from a logic low level to a logic high level by swinging from0V to about 3.3V. Thus, a midpoint of the transition of the first nodeNA is approximately about 1.65V. Since the operating power of the secondcircuit 120 is about 1.8V, a trigger point T1 of the second circuit 120is lowered below a midpoint of the trigger point of the first circuit110, i.e., at about 1.65V.

In response to the first node NA that transits from the logic high levelof about 3.3V to the logic low level of 0V, the second node NB transitsfrom the logic low level of 0V to the logic high level of about 1.8V.Since a trigger point of the second circuit 120 is low, the amount oftime required for the transition of the signal at the second node NBincreases. In response to the first node NA that transits from the logiclow level of 0V to the logic high level of about 3.3V, the second nodeNB transits from the logic high level of 1.8V to the logic low level of0V and the amount of time required for the transition of the second nodeNB decreases. As a result, there exists a transition interval Δ betweenthe midpoint of the transition from the logic low level to the logichigh level and the midpoint of the transition from the logic high levelto the logic low level. Such a transition interval causes skew.Moreover, occurrence of skew increases as the difference between theexternal power sources increases. Also, occurrence of skew changes theduty cycle of a signal at the second node NB.

Furthermore, the change in the duty cycle of the signal increases aset-up/hold time margin of the signal and reduces a valid window.Reduction in the valid window degrades performance of the chip.

Therefore, there is a need for an interface circuit that provides anoutput signal such that the amount of time required for transitions tothe logic high level and the logic low level are balanced and outputwithout minimized skew.

SUMMARY OF THE INVENTION

A level-down shifter is provided, comprising: a first circuit unithaving an input and output and connected to a first power node, thefirst circuit unit receives at its input an input signal that swingsfrom ground to a first voltage level; a second circuit unit having aninput and an output and connected to a second power node, the secondcircuit unit receives at its input the output of the first circuit unit;a third circuit unit having an input and an output and connected to thesecond power node, the third circuit unit receives at its input theinput signal; and a fourth circuit unit having an input and an outputand connected to the second power node, the fourth circuit unit receivesat its input the output of the third circuit unit and is connected tothe output of the second circuit unit, wherein a first voltage isapplied to the first power node and a second voltage is applied to thesecond power node. The first voltage is set at the first voltage level,and the first voltage level is higher than the second voltage.Preferably, the first power has the voltage level ranging from about2.0V to about 2.8V and the second power has a voltage level ranging fromabout 1.8V to about 2.2V.

The level-down shifter may comprise an inverter, which is driven by thefirst power and receives the input signal; a first PMOS transistor inthe second circuit line whose source is connected to the second powerand whose gate is connected to a drain of a second PMOS transistor, thesecond PMOS having its source connected to the second power and its gateconnected to a drain of the first PMOS transistor; a first NMOStransistor whose drain is connected to the drain of the first PMOStransistor, whose gate is connected to the input signal, and whosesource is connected to ground; and a second NMOS transistor whose drainis connected to a drain of the second PMOS transistor, whose gate isconnected to an output of the inverter, and whose source is connected toground.

An interface circuit is also provided, comprising a first inverter,which is driven by a first power and receives an input signal thatswings from ground to a voltage level of a second power; a secondinverter, which is driven by the second power and receives the inputsignal; a PMOS transistor whose source is connected to the first powerand whose gate is connected to an output of the first inverter; and anNMOS transistor whose source is connected to ground, whose gate isconnected to an output of the second inverter, and whose drain isconnected to a drain of the PMOS transistor, wherein a voltage level ofthe second power is higher than the voltage level of the first power.

According to another embodiment of the disclosure, an interface circuitcomprises a first power circuit having an input and an output, poweredby a first power and receives an input signal that swings from a groundvoltage level to a voltage level of the first power; a level-downshifter which converts the output of the first power circuit from avoltage level of the first power to an output having a voltage level ofa second power; and a second power circuit having an input and anoutput, powered by the second power and receives the output of thelevel-down shifter, and outputs an output signal that swings from groundto the voltage level of the second power, wherein the first power hasthe voltage level ranging from 2.0V to about 2.8V and the second powerhas a voltage level ranging from about 1.8V to about 2.2.V.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects of the present invention will become moreapparent by describing in detail exemplary embodiments thereof withreference to the attached drawings in which:

FIG. 1 shows signal transmission between a circuit operating at anexternal power and a circuit operating at an internal power;

FIG. 2 illustrates an interface circuit including a level-down shifter,according to a first embodiment of the present invention;

FIG. 3 illustrates an interface circuit including a level-down shifter,according to another embodiment of the present invention;

FIGS. 4 and 5 show an exemplary operation of the level-down shifter ofFIG. 3;

FIG. 6 illustrates an interface circuit including a level-down shifter,according to still another embodiment of the present invention;

FIGS. 7 and 8 shows an exemplary operation of the level-down shifter ofFIG. 6; and

FIG. 9 is a timing diagram showing signals of level-down shiftersaccording to embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the present invention will now be described more fullywith reference to the accompanying drawings in which reference numeralsrefer to like elements.

FIG. 2 illustrates an interface circuit including a level-down shifteraccording to a first embodiment of the present invention. Referring toFIG. 2, an interface circuit 200 includes an external power circuit unit210, a level-down shifter 220, and an internal power circuit unit 230.The external power circuit unit 210 is powered by an external power E.It receives an input signal IN, and outputs an output signal to a firstnode NA. The level-down shifter 220 includes a first path circuit 221and a second path circuit 225. the first path circuit 221 includes afirst circuit unit 222 and a second circuit unit 224 that are seriallyconnected between the first node NA and a fourth node ND. The secondpath circuit 225 includes a third circuit unit 226 and a fourth circuitunit 228 that are serially connected between the first node NA and thefourth node ND. The internal power circuit unit 230 is powered by aninternal power I. It receives a signal at a fourth node ND, and outputsan output signal OUT.

The first circuit unit 222 of the first path circuit 221 is connected toa first power node (not shown) suitable for application of a first powervoltage. The first power voltage is preferably applied from an externalsource. The second circuit unit 224 of the first path circuit 221 isconnected to a second power node, which is in turn connected to aninternal power I. The third circuit unit 226 and the fourth circuit unit228 of the second path circuit 225 are also connected to the secondpower node.

For purposes of explaining the operation of the interface circuit 200,it is preferred that the external power circuit unit 210, the firstthrough fourth circuit units 222, 224, 226, and 228, and the internalpower circuit unit 230 operate as an inverter. The voltage level of theexternal power E is set to about 2.8V and the voltage level of theinternal power I is set to about 1.8V. Bold-type signal waveformsindicated at nodes IN, NA, NB, NC, ND, and OUT are formed in response tothe transition of the input signal IN from the logic low level to thelogic high level. Thin-type signal waveforms indicated at nodes IN, NA,NB, NC, ND, and OUT are formed in response to the transition of theinput signal IN from the logic high level to the logic low level.

First, considering the bold-type signal waveforms, the input signal INtransits from the logic low level of 0V or ground to the logic highlevel of about 2.8V. The trigger point of the external power circuitunit 210 corresponds to the midpoint about 1.4V of the external power atabout E 2.8V. The first node NA transits from the logic high level ofabout 2.8V to the logic low level of 0V.

The trigger point of the first circuit unit 222 of the first pathcircuit unit 221 corresponds to the midpoint about 1.4V of the externalpower E, at about 2.8V, and the second node NB transits from the logiclow level of 0V to the logic high level of about 2.8V. The trigger pointof the second circuit unit 224 corresponds to the midpoint about 0.9V ofthe internal power I at about 1.8V. The second circuit unit 224 istriggered at a voltage level about 0.9V, which is lower than themidpoint of about 1.4V of the transition of the second node NB. Thus,the fourth node ND transits more quickly from the logic high level ofabout 1.8V to the logic low level of 0V.

The trigger point of the third circuit unit 226 of the second pathcircuit unit 225 corresponds to the midpoint of about 0.9V of theinternal power I at about 1.8V. The third circuit unit 226 is triggeredat the voltage level of about 0.9V, which is lower than the midpoint ofabout 1.4V of the transition of the first node NA. Thus, the third nodeNC transits slower from the logic low level of 0V to the logic highlevel of about 1.8V. The trigger point of the fourth circuit unit 228corresponds to the midpoint of the internal power I of about 1.8V. Thefourth circuit unit 228 is triggered at the midpoint of the transitionof the third node NC. Thus, the fourth node ND transits slower from thelogic high level of about 1.8V to the logic low level of 0V.

With the circuit connected as described, the fourth node ND transitsfrom about 1.8V to 0V faster via the first path circuit unit 221 ascompared to the second path circuit unit 225. The signal at the fourthnode ND is input to the internal power circuit unit 230. The internalpower circuit unit 230 generates an output signal OUT that transits fromthe logic low level of 0V to the logic high level of about 1.8V inresponse to the fourth node ND.

Nexr, considering the thin-type signal waveforms, the input signal INtransits from the logic high level of about 2.8V to the logic low levelof 0V. The trigger point of the external power circuit unit 210corresponds to the midpoint of the external power E at about 2.8V, andthe first node NA transits from the logic low level of 0V to the logichigh level of 2.8V.

The trigger point of the first circuit unit 222 of the path circuit unit221 corresponds to the midpoint 1.4V of the external power E, at about2.8V, and the second node NB transits from the logic high level of about2.8V to the logic low level of 0V. The trigger point of the secondcircuit unit 224 corresponds to the midpoint 0.9V of the internal powerI at about 1.8V. The second circuit unit 224 is triggered at the voltagelevel of 0.9V, which is lower than the midpoint 1.4V of the transitionof the second node NB. Thus, the fourth node ND transits slower from thelogic low level of 0V to the logic high level of about 1.8V

The trigger point of the third circuit unit 226 of the second pathcircuit unit 225 corresponds to the midpoint 0.9V of the internal powerI at about 1.8V. The third circuit unit 226 is triggered at the voltagelevel 0.9V, which is lower than the midpoint 1.4V of the transition ofthe first node NA. Thus, the third node NC transits faster from thelogic high level of about 1.8V to the logic low level of 0V. The triggerpoint of the fourth circuit unit 228 corresponds to the midpoint 0.9V ofthe internal power I at about 1.8V. The fourth circuit unit 228 istriggered at the midpoint 0.9V of the transition of the third node NC.Thus, the fourth node ND transits faster from the logic low level of 0Vto the logic high level of about 1.8V.

Here, the fourth node ND transits slower from 0V to 1.8V via the firstpath circuit unit 221 as compared to the second path circuit unit 225.

Therefore, referring to the waveforms of the input signal IN and theoutput signal OUT of the interface circuit 200 in this embodiment, inresponse to the input signal IN that transits from the logic low levelof 0V to the logic high level of about 2.8V and from the logic highlevel of about 2.8V to the logic low level of 0V, the output signal OUTtransits from the logic low level of 0V to the logic high level of about1.8V and from the logic high level of about 1.8V to the logic low levelof 0V. The midpoints of the two transition intervals are substantiallyidentical. Hence, the output signal OUT has minimal or no skew.

FIG. 3 illustrates an interface circuit 300 including a level-downshifter 320, according to another embodiment of the present invention.Referring to FIG. 3, the interface circuit 300 includes an externalpower circuit unit 310, the level-down shifter 320, and an internalpower circuit unit 330. The external power circuit unit 310 is driven byan external power E. It receives an input signal IN, and outputs theinput signal IN to the level-down shifter 320. The internal powercircuit unit 330 is driven by an internal power I. It receives an outputof the level-down shifter 330, and outputs an output signal OUT.

The level-down shifter 320 shifts a voltage level of the external powerE at node NE of the external power circuit unit 310 down to a voltagelevel of the internal power I. As shown, the level-down shifter 320includes an inverter 322, a first PMOS transistor 324, a second PMOStransistor 325, a first NMOS transistor 326, and a second NMOStransistor 327.

An input of the inverter 322 is connected to the node NE of the externalpower circuit unit 310. Sources of the first and second PMOS transistor324 and 325 are connected to an internal power voltage IVC. The gate ofthe first PMOS transistor 324 is connected to the drain of the secondPMOS transistor 325 and the gate of the second PMOS transistor 325 isconnected to the drain of the first PMOS transistor 324. A drain of thefirst NMOS transistor 326 is connected to a drain of the first PMOStransistor 324. A gate of the first NMOS transistor 326 is connected tothe output node NE of the external power circuit unit 310. A source ofthe first NMOS transistor 326 is connected to the ground voltage VSS. Adrain of the second NMOS transistor 327 is connected to a drain of thesecond PMOS transistor 325. A gate of the second NMOS transistor 327 isconnected to an output of the inverter 322. A source of the second NMOStransistor 327 is connected to the ground voltage VSS. The drains of thesecond PMOS transistor 325 and the second NMOS transistor 327 that areconnected with each other serve as an output node NH of the level-downshifter 320 and are input to the internal power circuit unit 330.

The operation of the interface circuit 300 according to this embodimentof the present invention is described based on a rising edge transitionand a falling edge transition of a signal at the node NE which is inputto the level-down shifter 320. referring to FIG. 4, a low-to-high(rising edge) transition at the output node NE is marked with a boldline. Assuming that the voltage level of the external power E is about2.8V, the output node NE undergoes the rising edge transition from 0V toabout 2.8V. The first NMOS transistor 326 of the level-down shifter 320is turned on when a gate-source voltage Vgs of the first NMOS transistor326 is more than a threshold voltage Vth of the first NMOS transistor326. For example, the first NMOS transistor 326 is turned on at atrigger point of about 0.6V of the node NE, which is marked with adotted line. Subsequently, a node NG transits to a logic low level of 0Vand the second PMOS transistor 325 is turned on. When the second PMOStransistor 325 is turned on, an output node NH of the level-down shifter320 transits to the voltage level near the internal power voltage IVC,e.g., a logic high level of about 1.8V.

In other words, once a voltage at the node NE rises to the thresholdvoltage Vth of the first NMOS transistor 326 while the output node NEswings from 0V to 2.8V, the output node NH of the level-down shifter 320transits quickly from 0V to about 1.8V.

Referring to FIG. 5 wherein the falling edge transition from high-to-lowis marked with a bold line. In response to the falling edge transitionof the output node NE from about 2.8V to 0V, a PMOS transistor 321 ofthe inverter 322 is turned on when a gate-source voltage Vgs of the PMOStransistor 321 is more than a threshold voltage Vth of the PMOStransistor 321. For example, the PMOS transistor 321 is turned on at atrigger point of about 2.2V while the output node NE swings from about2.8V to 0V. When the PMOS transistor 321 is turned on, an output node NFundergoes a rising edge transition from 0V to about 2.8V. A second NMOStransistor 327 of the level-down shifter 320 is turned on when agate-source voltage Vgs of the second NMOS transistor 327 is more than athreshold voltage Vth. For example, the second NMOS transistor 327 isturned on at a trigger point about 0.6V at the output node NF (seedotted line) while the output node NF swings from 0V to about 2.8V. Whenthe second NMOS transistor 327 is turned on, an output node NH of thelevel-down shifter 320 transits to a logic low level of near 0V orground voltage VSS.

In other words, in response to the transition from 0V to about 2.8V ofthe output node NE that is input to the level-down shifter 320, once thevoltage at the output node NE drops to a threshold voltage Vth of thePMOS transistor 321 and an output of the inverter 322 rises to thethreshold voltage Vth of the PMOS transistor 321, the output node NH ofthe level-down shifter 320 fast transits from about 1.8V to 0V.

FIG. 6 illustrates a circuit including a level-down shifter 600,according to another embodiment of the present invention.

Referring to FIG. 6, the interface circuit 600 includes an externalpower circuit unit 610, a level-down shifter 620, and an internal powercircuit unit 630. The interface circuit 600 converts an input signal INat the voltage level of the external power E into an output signal OUTat the voltage level of the internal power I.

The level-down shifter 620 includes a first inverter 622, a secondinverter 626, a PMOS transistor 624, and an NMOS transistor 628.

The first inverter 622 receives the output of the external power circuitunit 610 and is driven by the internal power I. The second inverter 626receives an output of the external power circuit unit 610 and is drivenby the external power E. A source of the PMOS transistor 624 isconnected to the internal power voltage IVC. A gate of the PMOStransistor 624 is connected to an output of the first inverter 622. Asource of the NMOS transistor 628 is connected to the ground voltageVSS. A gate of the NMOS transistor 628 is connected to an output of thesecond inverter 626. A drain of the NMOS transistor 628 is connected toa drain of the PMOS transistor 624.

FIG. 7 is a view showing an operation of the level-down shifter 620 ofFIG. 6 with a rising edge transition of an output node NI of theexternal power circuit unit 610.

Referring to FIG. 7, a low-to-high (rising edge) transition of theoutput node NI is marked with a bold line. Assuming that the voltagelevel of the external power E is about 2.8V, the output node NIundergoes a rising transition from 0V to about 2.8V. The NMOS transistor623 of the first inverter 622 of the level-down shifter 620 is turned onwhen a gate-source voltage Vgs of the NMOS transistor 623 is more than athreshold voltage Vth of the NMOS transistor 623. For example, the NMOStransistor 623 is turned on at a trigger point of about 0.6V of theoutput node NI (marked with a dotted line). Subsequently, a node NJtransits to a logic low level and the PMOS transistor 624 is turned on.When the PMOS transistor 624 is turned on, an output node NL of thelevel-down shifter 620 transits to a logic high level of about 1.8V,near the voltage level of internal power voltage IVC.

In other words, once a voltage at the node NI that is input to thelevel-down shifter 620 rises to a threshold voltage Vth of the NMOStransistor 623 while the node NI swings from 0V to 2.8V, the output nodeNL of the level-down shifter 620 transits quickly from 0V to 1.8V.

FIG. 8 shows an operation of the level-down shifter 620 with a fallingedge transition of the output node NE of the external power circuit unit610.

Referring to FIG. 8, a high-to-low (falling edge) transition of the nodeNI is marked with a bolded line. In response to a falling edgetransition of the node NI from about 2.8V to 0V, a PMOS transistor 625is turned on when a gate-source voltage Vgs of the PMOS transistor 625of the second inverter 626 is more than a threshold voltage Vth of thePMOS transistor 625, e.g., more than 0.6V. For example, the second PMOStransistor 625 is turned on at a trigger point of about 2.2V (dottedline) while the node NI swings from about 2.8V to 0V. When the PMOStransistor 625 is turned on, a node NK transits from 0V to about 2.8V.The NMOS transistor 628 is turned on when a gate-source voltage Vgs ofthe NMOS transistor 628 is more than a threshold voltage of the NMOStransistor 628, e.g., more than about 0.6V. For example, the NMOStransistor 628 is turned on at a trigger point about 0.6V (dotted line)while the node NK swings from 0V to about 2.8V. By the NMOS transistor628 that is turned on, an output node NL of the level-down shifter 620transits to a logic low level of 0V or the ground voltage VSS.

In other words, in response to the transition from 2.8V to 0V of thenode NI that is input to the level-down shifter 620, once the voltage atthe node NI drops to a threshold voltage Vth of the PMOS transistor 625and an output of the inverter 626 rises to the threshold voltage Vth ofthe PMOS transistor 625, the output node NL of the level-down shifter620 transits quickly from about 1.8V to 0V.

As such, once a voltage level of data input signal IN is output from anexternal power circuit unit rises to a threshold voltage Vth of thetransistor while the data input signal IN transits from a logic lowlevel to a logic high level, as shown in FIG. 9, level-down shifteraccording to embodiments of the present invention output a data outputsignal OUT that transits from a logic high level, which is equal to aninternal power voltage level, to a logic low level to an internal powercircuit unit. Once the voltage level of the data input signal IN dropsto the threshold voltage Vth of the transistor while the data inputsignal IN transits from a logic high level to a logic low level, thelevel-down shifters output the data output signal OUT that transits fromthe logic high level to the logic low level to the internal powercircuit unit. Therefore, a balanced output signal is transmitted with noor minimal skew between two circuit units operating at differentvoltages.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the invention as defined by the appended claims and theirequivalents.

1. A level-down shifter comprising: an inverter, which is driven by thefirst power and receives the input signal; a first PMOS transistor inthe second circuit unit whose source is connected to the second powerand whose gate is connected to a drain of a second PMOS transistor, thesecond PMOS having its source connected to the second power and its gateconnected to a drain of the first PMOS transistor; a first NMOStransistor whose drain is connected to the drain of the first PMOStransistor, whose gate is connected to the input signal, and whosesource is connected to ground; and a second NMOS transistor whose drainis connected to a drain of the second PMOS transistor, whose gate isconnected to an output of the inverter, and whose source is connected toground.
 2. The level-down shifter of claim 1, wherein a voltage level ofthe first power is higher than the voltage level of the second power. 3.An interface circuit comprising: a first power circuit having an inputand an output, powered by a first power and receives an input signalthat swings from a ground voltage level to a voltage level of the firstpower; a level-down shifter which converts the output of the first powercircuit from a voltage level of the first power to an output having avoltage level of a second power; and a second power circuit having aninput and an output, powered by the second power and receives the outputof the level-down shifter, and outputs an output signal that swings fromground to the voltage level of the second power, wherein the level-downshifter comprises: an inverter, which is driven by the first power andreceives the output of the first power circuit; a first PMOS transistorin the second circuit unit whose source is connected to the second powerand whose gate is connected to a drain of a second PMOS transistor, thesecond PMOS having its source connected to the second power and its gateconnected to a drain of the first PMOS transistor; a first NMOStransistor whose drain is connected to the drain of the first PMOStransistor, whose gate is connected to the output of the first powercircuit, and whose source is connected to ground; and a second NMOStransistor whose drain is connected to a drain of the second PMOStransistor, whose gate is connected to an output of the inverter, andwhose source is connected to ground.